#
# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: X11
#

#Create the project in the output directory
set_part xcvh1582-vsva3697-2MP-e-S

#Set the board part
set_property board_part xilinx.com:vhk158:part0:1.1 [current_project]

#####Read all sources for building the project#####

#Generate the system BD that has only CIPS and DDR NOCs
source ../sources/bd/bd.tcl

#Read the RTL files that has XPM NMUs and NSUs instantiated along with traffic generators and BRAM 
read_verilog {{../sources/rtl/top.v} {../sources/rtl/vnoc_to_hbm.v} {../sources/rtl/bli_to_hbm.v}}

#Generate the XCI files for BRAMs, Performance Traffic Generators and VIO IPs
source ../sources/ip/perf_axi_tg_pl_bli_to_hbm.tcl
source ../sources/ip/perf_axi_tg_pl_vnoc_to_hbm.tcl
source ../sources/ip/vio_pl_master_to_hbm.tcl

#Read the XDC files for creating NoC connection, setting its QoS settings and the aperture of XPM NSUs. 
read_xdc ../sources/xdc/noc_constraints.xdc

#Read the XDC files that has constraints for creating ILAs and for connecting them to debug hub in the design. This constraint is auto-generated by the tool based on "Set up Debug" flow.
read_xdc ../sources/xdc/top_debug.xdc

#####Set the USED_IN {synthesis_pre} for NoC constraints#####
set_property USED_IN {synthesis_pre} [get_files ../sources/xdc/noc_constraints.xdc]

#####Generate all targets : XCI/BD######
generate_target {synthesis implementation} [get_files {vio_pl_master_to_hbm.xci perf_axi_tg_pl_bli_to_hbm.xci perf_axi_tg_pl_vnoc_to_hbm.xci design_1.bd}]

synth_ip [get_ips {vio_pl_master_to_hbm perf_axi_tg_pl_bli_to_hbm perf_axi_tg_pl_vnoc_to_hbm design_1}]

##Updating the sourcefile set 
set_property source_mgmt_mode All [current_project]
update_compile_order

#Validate_noc happens in synth_design call. User can also call it explicitly 
synth_design -top top -part xcvh1582-vsva3697-2MP-e-S
write_checkpoint -force outputs/dcps/top_post_synth.dcp

#Place and Route
opt_design
#place_design
place_design -directive AggressiveExplore
route_design
write_checkpoint -force outputs/dcps/post_route.dcp
#Device Image Generation and LTX file Generation for debug
write_device_image -force outputs/top.pdi
write_debug_probes -force outputs/top.ltx

exit
